1. Background of the Invention
The present invention relates to a semiconductor packaging technique, and more particularly, to a 3-dimensional semiconductor packaging technique of connecting a plurality of chips by forming a hole vertically through a wafer without using a wire-bonding technique.
2. Description of the Related Art
Recent trends in micro-packaging technology reveal demand for inexpensive yet highly efficient, versatile yet smaller packaging. In order to meet such demand, a considerable amount of research has been conducted on new packaging techniques such as SoC (System-on-Chip), SiP (System-in-Package), MCM (Multi-Chip-Module), and SOP (System-on-Package) techniques. In particular, SOP technology mounting an SIP having a stacked structure and various components such as a hetero-material sensor that cannot be formed by a batch process, an electronic device, an SoC, and an optical device in a single package has attracted attention as a stacked semiconductor package suitable for an optical communication system as well as a wireless communication system. Demand for high-efficiency, high-density packages has led to a switchover from 2-dimensional stacked semiconductor packages to 3-dimensional stacked semiconductor packages. Many conventional packages have been tried in an attempt to electrically connect components using a through via, especially, a through silicon via (TSV). Also, a considerable amount of research has focused on a silicon carrier having a TSV in order to embody a fusion technique of integrating a hetero-device with a hetero-substrate.
Conventionally, manufacture of a TSV may include forming a via hole, depositing SiO2 or Si3N4, coating a seed layer required for a plating process, and forming a via core by plating the via hole with a metal such as copper (Cu). However, in a stacked semiconductor package using the TSV, a sidewall and bottom surface of the via hole are plated at the same time so that the via hole cannot be completely filled with Cu. In addition, since not only the via hole but also the via core have poor surface roughness, signal loss increases due to a skin effect and semiconductor characteristics of a silicon substrate, and waveform distortion and electrical crosstalk also happen. Accordingly, in order to enable high-speed signal transmission, signal power loss, waveform distortion, and electrical crosstalk must be minimized. Therefore, a method of depositing a SiO2 or Si3N4 layer using an oxidation process or a chemical vapor deposition (CVD) process is being widely employed. However, since this method makes the SiO2 or Si3N4 layer too thin, it is restricted to low-speed signal transmission systems or modules.